Impact of variations in different process parameters like, gate length, threshold voltage, oxide thickness etc. have been discussed in different components of digital circuits extensively in recent times. The various manufacturing effects on different process parameters have been demonstrated in [1] and [2]. Degradation in the operating frequencies by nearly 2X and increase in leakage power consumption by a factor of 3, have been demonstrated in FPGAs in [3]. Although static tuning of device parameters may counter such impacts to some extent, there are still variations that continue to impact the performance and power consumed by the chip. Consequently, such variations call for changes in the existing design tools and incorporation of variation awareness in those tools. In this paper, we propose a variation aware placement scheme in FPGAs and demonstrate the effectiveness of the scheme on Xilinx FPGAs and regular island style FPGAs. Our approach provides leakage benefits close to 14% on an average over different benchmark designs.