Based on the proposed reliability characterization model, reliability-bounded low-power design as a methodology to balance reliability enhancement and power reduction in chip design, for the first time, is illustrated. Voltage island partitioning and floorplanning for System-On-a-Chip (SOC) design is used as a case study for this reliability aware methodology. The proposed methodology partitions all SOC components into different voltage islands with power reduction and guaranteed system reliability. Experiments show that for a typical SOC the algorithm execution time is within several minutes while achieving 12% to 23% power reduction. Extended SOC algorithm partitions and floorplanns the voltage islands within 2.5 to 29.7 minutes and achieved 9.74% to 18.50% power reduction.