Partial and Dynamic Reconfiguration of FPGAs: a top down design methodology for an automatic implementation

I
ISVLSI
2006
IEEE Computer Society Annual Symposium on VLSI: Emerging VLSI Technologies and Architectures (ISVLSI'06)
Abstract - Partial and Dynamic Reconfiguration of FPGAs: a top down design methodology for an automatic implementation

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	Similar Articles Articles by Florent Berthelot Articles by Fabienne Nouvel

IEEE Computer Society Annual Symposium on VLSI: Emerging VLSI Technologies and Architectures (ISVLSI'06)

Karlsruhe, Germany

March 02-March 03

ISBN: 0-7695-2533-4

	ASCII Text	x
	Florent Berthelot, Fabienne Nouvel, "Partial and Dynamic Reconfiguration of FPGAs: a top down design methodology for an automatic implementation," VLSI, IEEE Computer Society Annual Symposium on, pp. 436-437, IEEE Computer Society Annual Symposium on VLSI: Emerging VLSI Technologies and Architectures (ISVLSI'06), 2006.

	BibTex	x
	@article{ 10.1109/ISVLSI.2006.71, author = {Florent Berthelot and Fabienne Nouvel}, title = {Partial and Dynamic Reconfiguration of FPGAs: a top down design methodology for an automatic implementation}, journal ={VLSI, IEEE Computer Society Annual Symposium on}, volume = {0}, year = {2006}, isbn = {0-7695-2533-4}, pages = {436-437}, doi = {http://doi.ieeecomputersociety.org/10.1109/ISVLSI.2006.71}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - VLSI, IEEE Computer Society Annual Symposium on TI - Partial and Dynamic Reconfiguration of FPGAs: a top down design methodology for an automatic implementation SN - 0-7695-2533-4 SP436 EP437 A1 - Florent Berthelot, A1 - Fabienne Nouvel, PY - 2006 KW - null VL - 0 JA - VLSI, IEEE Computer Society Annual Symposium on ER -

Florent Berthelot, CNRS UMR 6164 IETR-INSA, France

Fabienne Nouvel, CNRS UMR 6164 IETR-INSA, Rennes, France

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ISVLSI.2006.71

Dynamic and partial reconfiguration of FPGAs enables systems to adapt to changing demands. This paper concentrates on how to take into account specificities of partially reconfigurable components during the high level Adequation Algorithm Architecture process. We present a method which generates automatically the design for both partially and fixed parts of FPGAs.

Citation:

Florent Berthelot, Fabienne Nouvel, "Partial and Dynamic Reconfiguration of FPGAs: a top down design methodology for an automatic implementation," isvlsi, pp.436-437, IEEE Computer Society Annual Symposium on VLSI: Emerging VLSI Technologies and Architectures (ISVLSI'06), 2006

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