Optimisation of the SHA-2 Family of Hash Functions on FPGAs

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	Similar Articles Articles by Robert P. McEvoy Articles by Francis M. Crowe Articles by Colin C. Murphy Articles by William P. Marnane

IEEE Computer Society Annual Symposium on VLSI: Emerging VLSI Technologies and Architectures (ISVLSI'06)

Karlsruhe, Germany

March 02-March 03

ISBN: 0-7695-2533-4

	ASCII Text	x
	Robert P. McEvoy, Francis M. Crowe, Colin C. Murphy, William P. Marnane, "Optimisation of the SHA-2 Family of Hash Functions on FPGAs," VLSI, IEEE Computer Society Annual Symposium on, pp. 317-322, IEEE Computer Society Annual Symposium on VLSI: Emerging VLSI Technologies and Architectures (ISVLSI'06), 2006.

	BibTex	x
	@article{ 10.1109/ISVLSI.2006.70, author = {Robert P. McEvoy and Francis M. Crowe and Colin C. Murphy and William P. Marnane}, title = {Optimisation of the SHA-2 Family of Hash Functions on FPGAs}, journal ={VLSI, IEEE Computer Society Annual Symposium on}, volume = {0}, year = {2006}, isbn = {0-7695-2533-4}, pages = {317-322}, doi = {http://doi.ieeecomputersociety.org/10.1109/ISVLSI.2006.70}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - VLSI, IEEE Computer Society Annual Symposium on TI - Optimisation of the SHA-2 Family of Hash Functions on FPGAs SN - 0-7695-2533-4 SP317 EP322 A1 - Robert P. McEvoy, A1 - Francis M. Crowe, A1 - Colin C. Murphy, A1 - William P. Marnane, PY - 2006 KW - null VL - 0 JA - VLSI, IEEE Computer Society Annual Symposium on ER -

Robert P. McEvoy, University College Cork, Ireland

Francis M. Crowe, University College Cork, Ireland

Colin C. Murphy, University College Cork, Ireland

William P. Marnane, University College Cork, Ireland

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ISVLSI.2006.70

Hash functions play an important role in modern cryptography. This paper investigates optimisation techniques that have recently been proposed in the literature. A new VLSI architecture for the SHA-256 and SHA-512 hash functions is presented, which combines two popular hardware optimisation techniques, namely pipelining and unrolling. The SHA processors are developed for implementation on FPGAs, thereby allowing rapid prototyping of several designs. Speed/area results from these processors are analysed and are shown to compare favourably with other FPGA-based implementations, achieving the fastest data throughputs in the literature to date.

Citation:

Robert P. McEvoy, Francis M. Crowe, Colin C. Murphy, William P. Marnane, "Optimisation of the SHA-2 Family of Hash Functions on FPGAs," isvlsi, pp.317-322, IEEE Computer Society Annual Symposium on VLSI: Emerging VLSI Technologies and Architectures (ISVLSI'06), 2006

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