Exploiting the high-potential of nanoscale architectures requires that they be controlled by CMOS technology. Such an interface, a decoder, must control many nanowires (NWs) with a small number of meso-scale wires (MWs). Multiple types of decoder have been proposed, each of which can be modelled as embedding resistive switches in NWs. In this paper we present a general model for NW decoders and use it to specify the criteria they must meet to function correctly and be fault-tolerant. To illustrate the power of our model, we derive the first bounds on the size of a fault-tolerant randomized contact decoder.