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IEEE Computer Society Annual Symposium on VLSI: Emerging VLSI Technologies and Architectures (ISVLSI'06)
A new Multilevel Hierarchical MFPGA and its suitable configuration tools
Karlsruhe, Germany
March 02-March 03
ISBN: 0-7695-2533-4
ASCII Text
x 
 
Zied Marrakchi, Hayder Mrabet, Habib Mehrez, "A new Multilevel Hierarchical MFPGA and its suitable configuration tools," VLSI, IEEE Computer Society Annual Symposium on, pp. 263-268, IEEE Computer Society Annual Symposium on VLSI: Emerging VLSI Technologies and Architectures (ISVLSI'06), 2006.
 
 
BibTex
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@article{ 10.1109/ISVLSI.2006.6,
author = {Zied Marrakchi and Hayder Mrabet and Habib Mehrez},
title = {A new Multilevel Hierarchical MFPGA and its suitable configuration tools},
journal ={VLSI, IEEE Computer Society Annual Symposium on},
volume = {0},
year = {2006},
isbn = {0-7695-2533-4},
pages = {263-268},
doi = {http://doi.ieeecomputersociety.org/10.1109/ISVLSI.2006.6},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - VLSI, IEEE Computer Society Annual Symposium on
TI - A new Multilevel Hierarchical MFPGA and its suitable configuration tools
SN - 0-7695-2533-4
SP263
EP268
A1 - Zied Marrakchi,
A1 - Hayder Mrabet,
A1 - Habib Mehrez,
PY - 2006
KW - null
VL - 0
JA - VLSI, IEEE Computer Society Annual Symposium on
ER -
 
Zied Marrakchi, Universit e Paris 6, Pierre et Marie Curie
Hayder Mrabet, Universite Paris 6, Pierre et Marie Curie
Habib Mehrez, Universite Paris 6, Pierre et Marie Curie
In this paper we evaluate a new multilevel hierarchical MFPGA. The specific architecture includes two unidirectional programmable networks: A downward network based on the Butterfly-Fat-Tree topology, and a special rising network. New tools are developed to place and route several benchmark circuits on this architecture. Comparison with the traditional symmetric, manhattan mesh architecture shows that MFPGA can implement circuits with fewer switches and a smaller area.
Citation:
Zied Marrakchi, Hayder Mrabet, Habib Mehrez, "A new Multilevel Hierarchical MFPGA and its suitable configuration tools," isvlsi, pp.263-268, IEEE Computer Society Annual Symposium on VLSI: Emerging VLSI Technologies and Architectures (ISVLSI'06), 2006
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