IEEE Computer Society Annual Symposium on VLSI: Emerging VLSI Technologies and Architectures (ISVLSI'06) Low Power Layered Space-Time Channel Detector Architecture for MIMO Systems Karlsruhe, Germany March 02-March 03 ISBN: 0-7695-2533-4
This paper presents the low power implementation of a Maximum Likelihood (ML) based detector used in the receiver part of a Multiple Input and Multiple Output (MIMO) systems. Low power is mainly achieved through complexity reduction of the ML detector. In particular, Manhattan metric approach is proposed for removing the need for the use of multipliers in the architecture, leading to significant complexity reduction in the ML detector implementation with only 0.7 dB loss in the Bit Error Rate (BER) performance. Results are presented showing that our ML detector achieves 29% saving in area and 34.4% saving in power consumption compared to conventional implementations.
Citation:
T. Takahashi, A.T. Erdogan, T. Arslan, J. H. Han, "Low Power Layered Space-Time Channel Detector Architecture for MIMO Systems," isvlsi, pp.444-445, IEEE Computer Society Annual Symposium on VLSI: Emerging VLSI Technologies and Architectures (ISVLSI'06), 2006 Usage of this product signifies your acceptance of the Terms of Use. | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
Digg
Furl
Spurl
Blink
Simpy
Google
Del.icio.us
Y!MyWeb