3D integration is a new technology that will greatly increase transistor density while providing faster on-chip communication. 3D integration stacks multiple die connected with a very high-density and low-latency interface which provides increased device density and the ability to place and route in the third dimension. While past studies have explored 3D integrated onchip caches, this research explores the implementation of register files, which have very different capacity and bandwidth requirements. Partitioning the register file across multiple die reduces the lengths of many critical wires, which provides both latency and energy benefits. In particular, a 3D implementation of 256-entry physical register file in a two-die stack achieves a 24.1% latency improvement with a simultaneous energy reduction of 58.5%, while a four-die version achieves a 36.0% latency improvement with a 58.2% energy reduction. Our results demonstrate that 3D integration is a promising approach for improving both the performance and power of wire-dominated circuits.