A new low voltage swing circuit technique based on a dual threshold voltage CMOS technology is presented in this paper for simultaneously reducing active and standby mode power consumption and enhancing evaluation speed and noise immunity in domino logic circuits. The proposed circuit technique modifies both the upper and lower boundaries of the voltage swing at the dynamic node. Meanwhile, full voltage swing signals are maintained at inputs and outputs for robust and high speed operation. Power supply, ground, and threshold voltages are simultaneously optimized to minimize the power-delay product (PDP). The proposed technique reduces the PDP by up to 51.9% as compared to standard full-swing circuits in a 45nm CMOS technology. The active mode power consumption is reduced by up to 40.4% due to lower switching power required to charge/discharge the dynamic node. Furthermore, the evaluation speed and noise immunity are enhanced by up to 19.4% and 39.1%, respectively, as compared to standard fullswing circuits. The proposed low swing technique also reduces the idle mode leakage power consumption by up to 84.2% in the high fan-in domino gates.