IEEE Computer Society Annual Symposium on VLSI: Emerging VLSI Technologies and Architectures (ISVLSI'06) High performance service-time-stamp computation for WFQ IP packet scheduling Karlsruhe, Germany March 02-March 03 ISBN: 0-7695-2533-4
In this paper the design and implementation of a unique service-time-stamp computation circuit, called the finishing tag, for WFQ based packet scheduling is presented. The implementation is based on UMC 130nm standard cell technology, and placed and routed using Cadence SoC encounter. The design targets the development of programmable IP packet scheduling circuits for next generation network processing platforms for line-rates beyond 200Gbps.
Citation:
C. McKillen, S. Sezer, Xin Yang, "High performance service-time-stamp computation for WFQ IP packet scheduling," isvlsi, pp.65-70, IEEE Computer Society Annual Symposium on VLSI: Emerging VLSI Technologies and Architectures (ISVLSI'06), 2006 Usage of this product signifies your acceptance of the Terms of Use. | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||