Globally Asynchronous Locally Synchronous Wrapper Circuit based on Clock Gating

I
ISVLSI
2006
IEEE Computer Society Annual Symposium on VLSI: Emerging VLSI Technologies and Architectures (ISVLSI'06)
Abstract - Globally Asynchronous Locally Synchronous Wrapper Circuit based on Clock Gating

	This Article
	Subscribers, please Login Purchase article: $19 PDF IEEE Xplore Subscribers RSS feed
	Share
	Email this Article to a friend
	Bibliographic References
	ASCII Text BibTex RefWorks Procite/RefMan
	Add to:
	Digg Furl Spurl Blink Simpy Google Del.icio.us Y!MyWeb
	Search
	Similar Articles Articles by Esmail Amini Articles by Mehrdad Najibi Articles by Hossein Pedram

IEEE Computer Society Annual Symposium on VLSI: Emerging VLSI Technologies and Architectures (ISVLSI'06)

Karlsruhe, Germany

March 02-March 03

ISBN: 0-7695-2533-4

	ASCII Text	x
	Esmail Amini, Mehrdad Najibi, Hossein Pedram, "Globally Asynchronous Locally Synchronous Wrapper Circuit based on Clock Gating," VLSI, IEEE Computer Society Annual Symposium on, pp. 193-199, IEEE Computer Society Annual Symposium on VLSI: Emerging VLSI Technologies and Architectures (ISVLSI'06), 2006.

	BibTex	x
	@article{ 10.1109/ISVLSI.2006.48, author = {Esmail Amini and Mehrdad Najibi and Hossein Pedram}, title = {Globally Asynchronous Locally Synchronous Wrapper Circuit based on Clock Gating}, journal ={VLSI, IEEE Computer Society Annual Symposium on}, volume = {0}, year = {2006}, isbn = {0-7695-2533-4}, pages = {193-199}, doi = {http://doi.ieeecomputersociety.org/10.1109/ISVLSI.2006.48}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - VLSI, IEEE Computer Society Annual Symposium on TI - Globally Asynchronous Locally Synchronous Wrapper Circuit based on Clock Gating SN - 0-7695-2533-4 SP193 EP199 A1 - Esmail Amini, A1 - Mehrdad Najibi, A1 - Hossein Pedram, PY - 2006 KW - null VL - 0 JA - VLSI, IEEE Computer Society Annual Symposium on ER -

Esmail Amini, Amirkabir University of Technology, Tehran, IRAN.

Mehrdad Najibi, Amirkabir University of Technology, Tehran, IRAN.

Hossein Pedram, Amirkabir University of Technology, Tehran, IRAN.

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ISVLSI.2006.48

One major issue in designing image processors is to design a memory system that supports parallel access with a simple interconnection network. This paper presents a design methodology for a logic-in-memory architecture where each of memory modules is connected to its dedicated processing element(PE). An efficient memory allocation to minimize the number of memory modules and PEs under a time constraint is proposed based on regularity.

Citation:

Esmail Amini, Mehrdad Najibi, Hossein Pedram, "Globally Asynchronous Locally Synchronous Wrapper Circuit based on Clock Gating," isvlsi, pp.193-199, IEEE Computer Society Annual Symposium on VLSI: Emerging VLSI Technologies and Architectures (ISVLSI'06), 2006

Peer Review Notice | Give Us Feedback

Usage of this product signifies your acceptance of the Terms of Use.