Recent research in the area of Application Specific Instruction- set Processors (ASIPs) has focused on automatic configuration. In this paper, we propose a novel approach for selecting the size of the branch predictor pattern history table (PHT) to reduce the overall power dissipation for a specific application. This approach uses a fast configuration approach that dynamically measures aliasing for all PHT sizes in parallel and then uses a cost function that relates aliasing to power dissipation. Results show that by configuring the PHT using our approach, the overall power reduction closely matches that achievable with a "perfect" configuration.