This work addresses the problem of power consumption in networks-on-chip (NoCs). It investigates the reduction of dynamic power consumption through the reduction of transition activity using data coding techniques. Power macromodels for various NoC modules were built, allowing the estimation of the power consumption as a function of the transition activity at each module?s inputs. Such macromodels were embedded in a system model and a series of simulations were performed, aiming to analyze the trade-off between the power savings due to coding techniques versus the power consumption overhead due to the encoding and decoding modules.

A network-on-chip (NoC) is an infrastructure essentially composed of routers interconnected by communication channels. It is suitable to support the GALS paradigm, since it provides asynchronous communication, high scalability, reusability and reliability [1][2].

The growing market for portable battery-powered devices adds a third dimension (power) to the previously two-dimensional (speed, area) VLSI design space [3]. NoCs are not particularly efficient in power consumption. They solve the problem of high capacitances in wires and, consequently, the power consumption in long lines, but on the other hand the power consumed by the router modules is not negligible.