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IEEE Computer Society Annual Symposium on VLSI: Emerging VLSI Technologies and Architectures (ISVLSI'06)
A Low Power Pipelined Maximum Likelihood Detector for 4x4 QPSK MIMO Wireless Communication Systems
Karlsruhe, Germany
March 02-March 03
ISBN: 0-7695-2533-4
J.H Han, University of Edinburgh, UK
A.T Erdogan, Institute of System Level Integration, Alba Campus, UK
T. Arslan, Institute of System Level Integration, Alba Campus, UK
The authors present a maximum likelihood (ML) detector for multiple-input multiple-output (MIMO) wireless communication systems. The ML detector has been specifically designed to reduce the implementation complexity without signzficant degradation in bit error rate (BER) performance. In order to identify the optimized fixed-point representation, the ML detector has been simuluted with various representations for the received data. The computation process of the channel matrix and constellation symbols in ML detector is simplifiedd by using normalized symbols. Simulation results are provided showing 42% saving in area usage and 68% saving in power consumption compared to a conveniional architecture.
Citation:
J.H Han, A.T Erdogan, T. Arslan, "A Low Power Pipelined Maximum Likelihood Detector for 4x4 QPSK MIMO Wireless Communication Systems," isvlsi, pp.185-192, IEEE Computer Society Annual Symposium on VLSI: Emerging VLSI Technologies and Architectures (ISVLSI'06), 2006
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