Dual-Mode High-Speed Low-Energy Binary Addition

	This Article
	Subscribers, please Login Purchase article: $19 PDF IEEE Xplore Subscribers RSS feed
	Share
	Email this Article to a friend
	Bibliographic References
	ASCII Text BibTex RefWorks Procite/RefMan
	Add to:
	Digg Furl Spurl Blink Simpy Google Del.icio.us Y!MyWeb
	Search
	Similar Articles Articles by Johannes Grad Articles by James E. Stine

IEEE Computer Society Annual Symposium on VLSI: Emerging VLSI Technologies and Architectures (ISVLSI'06)

Karlsruhe, Germany

March 02-March 03

ISBN: 0-7695-2533-4

	ASCII Text	x
	Johannes Grad, James E. Stine, "Dual-Mode High-Speed Low-Energy Binary Addition," VLSI, IEEE Computer Society Annual Symposium on, pp. 428-429, IEEE Computer Society Annual Symposium on VLSI: Emerging VLSI Technologies and Architectures (ISVLSI'06), 2006.

	BibTex	x
	@article{ 10.1109/ISVLSI.2006.37, author = {Johannes Grad and James E. Stine}, title = {Dual-Mode High-Speed Low-Energy Binary Addition}, journal ={VLSI, IEEE Computer Society Annual Symposium on}, volume = {0}, year = {2006}, isbn = {0-7695-2533-4}, pages = {428-429}, doi = {http://doi.ieeecomputersociety.org/10.1109/ISVLSI.2006.37}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - VLSI, IEEE Computer Society Annual Symposium on TI - Dual-Mode High-Speed Low-Energy Binary Addition SN - 0-7695-2533-4 SP428 EP429 A1 - Johannes Grad, A1 - James E. Stine, PY - 2006 KW - null VL - 0 JA - VLSI, IEEE Computer Society Annual Symposium on ER -

Johannes Grad, Illinois Institute of Technology, Chicago

James E. Stine, Oklahoma State University

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ISVLSI.2006.37

Sparse tree adders are a common choice for the implementation of high performance binary addition. However, for constant supply voltage they have constant energy consumption regardless of the operating frequency. This paper presents a dual-mode sparse tree adder that offers a lowspeed low-energy mode. This is achieved by disabling the prefix tree in the low-speed mode. Simulation results using extracted mask layouts show a reduction in energy consumption in the low-speed mode by a factor of 3.6 in static CMOS and a factor of 2.3 in domino logic.

Citation:

Johannes Grad, James E. Stine, "Dual-Mode High-Speed Low-Energy Binary Addition," isvlsi, pp.428-429, IEEE Computer Society Annual Symposium on VLSI: Emerging VLSI Technologies and Architectures (ISVLSI'06), 2006

Peer Review Notice | Give Us Feedback

Usage of this product signifies your acceptance of the Terms of Use.