With advances in process technology, the feature sizes are decreasing, which leads to higher defect densities. More sophisticated techniques, at increased costs are required to avoid defects. If nanotechnology based fabrications are applied, the yield may even go down to zero, as avoiding defects during fabrication will not be a feasible option. Hence, future architectures have to be defect-tolerant. Most of the current defect-tolerance schemes introduce redundancy in architecture to combat defects. Alternatively we can introduce defect tolerance in the design-flow.

In this paper we analyze the bottlenecks faced by current design-methodologies while addressing defect tolerance. We study the performance of present Place and Route tools on a defective fabric in terms of area and critical delay penalty, and explore routing aware placement in this context. We have proposed a new cost function, CA-RISA for improving the performance in a defect-aware environment.