One of the problems associated with the ever-increasing level of on-chip integration in CMOS is excessive power consumption [3]. While dynamic power consumption currently is the dominating component of power, leakage energy consumption is becoming increasingly important and projected to be the main power roadblock in future CMOS designs [5]. Large on-chip memory components are particularly problematic from a leakage perspective since they accommodate a large number of transistors. Current proposals for reducing leakage consumption of memory components focus exclusively on cache architectures. While caches are being increasingly used in embedded computing, software-managed memories (SMMs) have also found their ways into commercial products. For example, both StrongArm [1] and IBM?s Cell chip multiprocessor [2] contain software-managed memories, contents of which can be explicitly controlled by a compiler. Our goal in this paper is to demonstrate that an optimizing compiler can be very successful in reducing leakage energy consumption of on-chip SMMs for array-dominated embedded applications.