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IEEE Computer Society Annual Symposium on VLSI: Emerging VLSI Technologies and Architectures (ISVLSI'06)
A Flexible Architecture For Block Turbo Decoders Using BCH Or Reed-Solomon Components Codes
Karlsruhe, Germany
March 02-March 03
ISBN: 0-7695-2533-4
ASCII Text
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Erwan PIRIOU, Christophe JEGO, Patrick ADDE, Michel JEZEQUEL, "A Flexible Architecture For Block Turbo Decoders Using BCH Or Reed-Solomon Components Codes," VLSI, IEEE Computer Society Annual Symposium on, pp. 430-431, IEEE Computer Society Annual Symposium on VLSI: Emerging VLSI Technologies and Architectures (ISVLSI'06), 2006.
 
 
BibTex
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@article{ 10.1109/ISVLSI.2006.2,
author = {Erwan PIRIOU and Christophe JEGO and Patrick ADDE and Michel JEZEQUEL},
title = {A Flexible Architecture For Block Turbo Decoders Using BCH Or Reed-Solomon Components Codes},
journal ={VLSI, IEEE Computer Society Annual Symposium on},
volume = {0},
year = {2006},
isbn = {0-7695-2533-4},
pages = {430-431},
doi = {http://doi.ieeecomputersociety.org/10.1109/ISVLSI.2006.2},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
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TY - CONF
JO - VLSI, IEEE Computer Society Annual Symposium on
TI - A Flexible Architecture For Block Turbo Decoders Using BCH Or Reed-Solomon Components Codes
SN - 0-7695-2533-4
SP430
EP431
A1 - Erwan PIRIOU,
A1 - Christophe JEGO,
A1 - Patrick ADDE,
A1 - Michel JEZEQUEL,
PY - 2006
KW - null
VL - 0
JA - VLSI, IEEE Computer Society Annual Symposium on
ER -
 
Erwan PIRIOU, GET/ENST Bretagne, CNRS TAMCIC UMR 2872 , Brest, France
Christophe JEGO, GET/ENST Bretagne, CNRS TAMCIC UMR 2872 , Brest, France
Patrick ADDE, GET/ENST Bretagne, CNRS TAMCIC UMR 2872 , Brest, France
Michel JEZEQUEL, GET/ENST Bretagne, CNRS TAMCIC UMR 2872 , Brest, France
In this paper, the first flexible architecture dedicated to block turbo decoders is presented. The major innovation concerns the component code that is used by the block turbo code. In fact, our architecture is able to decode BCH and Reed-Solomon codes with single or double correction power. To the authors? knowledge, this is the first architecture implementing Reed-Solomon block turbo codes. This approach makes it possible to select the block turbo decoder architecture using optimum component codes in any circumstance. Our flexible elementary SISO decoder is dedicated to extended binary BCH codes (32,26) and (32,21) and to non-extended Reed-Solomon codes (31,29) and (31,27). Experimentation has been done on a Stratix-based NIOS development board.
Citation:
Erwan PIRIOU, Christophe JEGO, Patrick ADDE, Michel JEZEQUEL, "A Flexible Architecture For Block Turbo Decoders Using BCH Or Reed-Solomon Components Codes," isvlsi, pp.430-431, IEEE Computer Society Annual Symposium on VLSI: Emerging VLSI Technologies and Architectures (ISVLSI'06), 2006
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