Today?s information society demands access to huge amount of data anywhere and data any time. Hence wireless communications is a key technology. In such systems bandwidth and transmission power are critical resources. Thus advanced communications systems have to rely on sophisticated error correction schemes (FEC). Turbo- and LDPC codes belong to the most efficient error correction schemes known by now. However the iterative decoding nature of these codes imply big implementation challenges w.r.t. throughput, latency and low energy. Moreover future communication systems require flexibility. Thus we have to tradeoff flexibility versus implementation costs. In this talk we discuss the design space for Turboand LDPC decoders and compare different implementation alternatives. Moreover we show the need of a design methodology which have to consider code-design and architecture development in a unified way. We discuss this challenge on the base of 3GPP Turbodecoders and DVB-S2 LDPC decoders.