A VLSI GFP Frame Delineation Circuit

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IEEE Computer Society Annual Symposium on VLSI: Emerging VLSI Technologies and Architectures (ISVLSI'06)

Karlsruhe, Germany

March 02-March 03

ISBN: 0-7695-2533-4

	ASCII Text	x
	Ciaran Toal, Sakir Sezer, Xin Yang, "A VLSI GFP Frame Delineation Circuit," VLSI, IEEE Computer Society Annual Symposium on, pp. 454-455, IEEE Computer Society Annual Symposium on VLSI: Emerging VLSI Technologies and Architectures (ISVLSI'06), 2006.

	BibTex	x
	@article{ 10.1109/ISVLSI.2006.14, author = {Ciaran Toal and Sakir Sezer and Xin Yang}, title = {A VLSI GFP Frame Delineation Circuit}, journal ={VLSI, IEEE Computer Society Annual Symposium on}, volume = {0}, year = {2006}, isbn = {0-7695-2533-4}, pages = {454-455}, doi = {http://doi.ieeecomputersociety.org/10.1109/ISVLSI.2006.14}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - VLSI, IEEE Computer Society Annual Symposium on TI - A VLSI GFP Frame Delineation Circuit SN - 0-7695-2533-4 SP454 EP455 A1 - Ciaran Toal, A1 - Sakir Sezer, A1 - Xin Yang, PY - 2006 KW - null VL - 0 JA - VLSI, IEEE Computer Society Annual Symposium on ER -

Ciaran Toal, Queen?s University Belfast, Northern

Sakir Sezer, Queen?s University Belfast, Northern

Xin Yang, Queen?s University Belfast, Northern

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ISVLSI.2006.14

This paper presents the design and study of a circuit architecture able to perform 16Gbps GFP frame delineation with single bit error correction using UMC 130nm standard cell technology. The design targets the development of a hard macro core for the design of next generation network processing platforms.

Citation:

Ciaran Toal, Sakir Sezer, Xin Yang, "A VLSI GFP Frame Delineation Circuit," isvlsi, pp.454-455, IEEE Computer Society Annual Symposium on VLSI: Emerging VLSI Technologies and Architectures (ISVLSI'06), 2006

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