A Regular Layout Approach for ASICs

	This Article
	Subscribers, please Login Purchase article: $19 PDF IEEE Xplore Subscribers RSS feed
	Share
	Email this Article to a friend
	Bibliographic References
	ASCII Text BibTex RefWorks Procite/RefMan/Endnote
	Add to:
	Digg Furl Spurl Blink Simpy Google Del.icio.us Y!MyWeb
	Search
	Similar Articles Articles by Claudio Menezes Articles by Cristina Meinhardt Articles by Ricardo Reis Articles by Reginaldo Tavares

IEEE Computer Society Annual Symposium on VLSI: Emerging VLSI Technologies and Architectures (ISVLSI'06)

Karlsruhe, Germany

March 02-March 03

ISBN: 0-7695-2533-4

	ASCII Text	x
	Claudio Menezes, Cristina Meinhardt, Ricardo Reis, Reginaldo Tavares, "A Regular Layout Approach for ASICs," VLSI, IEEE Computer Society Annual Symposium on, pp. 424-425, IEEE Computer Society Annual Symposium on VLSI: Emerging VLSI Technologies and Architectures (ISVLSI'06), 2006.

	BibTex	x
	@article{ 10.1109/ISVLSI.2006.11, author = {Claudio Menezes and Cristina Meinhardt and Ricardo Reis and Reginaldo Tavares}, title = {A Regular Layout Approach for ASICs}, journal ={VLSI, IEEE Computer Society Annual Symposium on}, volume = {0}, year = {2006}, isbn = {0-7695-2533-4}, pages = {424-425}, doi = {http://doi.ieeecomputersociety.org/10.1109/ISVLSI.2006.11}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - VLSI, IEEE Computer Society Annual Symposium on TI - A Regular Layout Approach for ASICs SN - 0-7695-2533-4 SP424 EP425 A1 - Claudio Menezes, A1 - Cristina Meinhardt, A1 - Ricardo Reis, A1 - Reginaldo Tavares, PY - 2006 KW - null VL - 0 JA - VLSI, IEEE Computer Society Annual Symposium on ER -

Claudio Menezes, Instituto de Inform?tica -UFRGS, Brazil

Cristina Meinhardt, Instituto de Inform?tica -UFRGS, Brazil

Ricardo Reis, Instituto de Inform?tica -UFRGS, Brazil

Reginaldo Tavares, Universidade Estadual do Rio Grande do Sul

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ISVLSI.2006.11

This paper presents a regular layout approach addressing the need of a more predictable circuit performance and DFM. Experiments were done using a regular matrix of cells composed by 2-input NAND gates. The regular layout approach considers some strategies to improve the predictability of connections and the routability of circuits. Initial experiments show that this approach should improve performance when compared with a standard cell approach.

Citation:

Claudio Menezes, Cristina Meinhardt, Ricardo Reis, Reginaldo Tavares, "A Regular Layout Approach for ASICs," isvlsi, pp.424-425, IEEE Computer Society Annual Symposium on VLSI: Emerging VLSI Technologies and Architectures (ISVLSI'06), 2006

Peer Review Notice | Give Us Feedback

Usage of this product signifies your acceptance of the Terms of Use.