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IEEE Computer Society Annual Symposium on VLSI: Emerging VLSI Technologies and Architectures (ISVLSI'06)
A Parallel Architecture for Hardware Face Detection
Karlsruhe, Germany
March 02-March 03
ISBN: 0-7695-2533-4
T. Theocharides, University of Cyprus
N. Vijaykrishnan, Penn State University
M. J. Irwin, Penn State University
Face detection is a very important application in the field of machine vision. In this paper, we present a scalable parallel architecture which performs face detection using the AdaBoost algorithm. Experimental results show that the proposed architecture can detect faces with the same accuracy as the software implementation, on real-time video at a frame rate of 52 frames per second.
Citation:
T. Theocharides, N. Vijaykrishnan, M. J. Irwin, "A Parallel Architecture for Hardware Face Detection," isvlsi, pp.452-453, IEEE Computer Society Annual Symposium on VLSI: Emerging VLSI Technologies and Architectures (ISVLSI'06), 2006
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