Wire Length Distribution Model Considering Core Utilization for System on Chip

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IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design (ISVLSI'05)

Wire Length Distribution Model Considering Core Utilization for System on Chip (PDF)

Tampa, Florida

May 11-May 12

ISBN: 0-7695-2365-X

	ASCII Text	x
	Takanori Kyogoku, Junpei Inoue, Hidenari Nakashima, Takumi Uezono, Kenichi Okada, Kazuya Masu, "Wire Length Distribution Model Considering Core Utilization for System on Chip," VLSI, IEEE Computer Society Annual Symposium on, pp. 276-277, IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design (ISVLSI'05), 2005.

	BibTex	x
	@article{ 10.1109/ISVLSI.2005.76, author = {Takanori Kyogoku and Junpei Inoue and Hidenari Nakashima and Takumi Uezono and Kenichi Okada and Kazuya Masu}, title = {Wire Length Distribution Model Considering Core Utilization for System on Chip}, journal ={VLSI, IEEE Computer Society Annual Symposium on}, volume = {0}, year = {2005}, isbn = {0-7695-2365-X}, pages = {276-277}, doi = {http://doi.ieeecomputersociety.org/10.1109/ISVLSI.2005.76}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - VLSI, IEEE Computer Society Annual Symposium on TI - Wire Length Distribution Model Considering Core Utilization for System on Chip SN - 0-7695-2365-X SP276 EP277 A1 - Takanori Kyogoku, A1 - Junpei Inoue, A1 - Hidenari Nakashima, A1 - Takumi Uezono, A1 - Kenichi Okada, A1 - Kazuya Masu, PY - 2005 KW - Wire Length Distribution KW - core utilization KW - SoC KW - layout-area allocation VL - 0 JA - VLSI, IEEE Computer Society Annual Symposium on ER -

Takanori Kyogoku, Tokyo Institute of Technology

Junpei Inoue, Tokyo Institute of Technology

Hidenari Nakashima, Tokyo Institute of Technology

Takumi Uezono, Tokyo Institute of Technology

Kenichi Okada, Tokyo Institute of Technology

Kazuya Masu, Tokyo Institute of Technology

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ISVLSI.2005.76

This paper presents a new model to estimate wire length distribution (WLD) of system on chip (SoC). The WLD represents a correlation between wire length and the number of interconnect, and we can predict power consumption, maximum clock frequency, chip size, etc with the WLD. The proposed model provides a WLD considering each core utilization of several macro blocks in a system LSI. We present an optimization method to determine each core utilization.

Index Terms:

Wire Length Distribution, core utilization, SoC, layout-area allocation

Citation:

Takanori Kyogoku, Junpei Inoue, Hidenari Nakashima, Takumi Uezono, Kenichi Okada, Kazuya Masu, "Wire Length Distribution Model Considering Core Utilization for System on Chip," isvlsi, pp.276-277, IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design (ISVLSI'05), 2005

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