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IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design (ISVLSI'05)
Towards Integration of Quadratic Placement and Pin Assignment
Tampa, Florida
May 11-May 12
ISBN: 0-7695-2365-X
Jurjen Westra, Eindhoven University of Technology
Patrick Groeneveld, Eindhoven University of Technology

Pins serve as both the logical and physical interface between two levels in a hierarchical flow. Pin assignment is the placement of pins on the boundary of a chip or macro. Proper pin placement has a large influence on wire length. Experiments indicate a spread in wire length up to over 20%.

To address the pin assignment problem, a modification to the well-known and widely used quadratic placement is introduced. This modification allows for the integration between pin assignment and global placement. Wire length within macros is minimized, while top-level considerations such as the relative position of macro and clusters of cells are taken into account in the form of a side assignment.

As indicated by experimental results, integration is promising. More research is necessary to fully exploit the ideas in this paper, and assess the practical impact of the approach.

Citation:
Jurjen Westra, Patrick Groeneveld, "Towards Integration of Quadratic Placement and Pin Assignment," isvlsi, pp.284-286, IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design (ISVLSI'05), 2005
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