Recent increases in the gate capacity of current chips are beginning to exacerbate the problems caused by the use of a global clock. Motivated by the gravity of this problem, designers are currently considering clockless circuits as a viable alternative. Unfortunately, at this time, there is no unified design methodology to support the design and verification of clockless circuits. Since most designers are familiar with existing CAD tools for clocked circuits, an ideal solution would be a design methodology that would exploit these tools as much as possible. However, implemented mostly as fine-grain pipelines, the majority of these clockless circuits are not suitable to synthesize large datapaths. This paper reviews a previously introduced clockless design technique, called self-resetting stage logic (SRSL), which is suitable for synthesizing datapaths [1, 2]. Based on SRSL pipelining techniques, a new design methodology is proposed to synthesize clockless designs.