IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design (ISVLSI'05) Tampa, Florida May 11-May 12 ISBN: 0-7695-2365-X
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ISVLSI.2005.7
The clock period in conventional pipeline scheme is proportional to the maximum delay while in hybrid wave-pipelining it is proportional to the maximum delay difference. An 8 ?8-bit hybrid wave-pipeline multiplier using carry-save adder technique is described. The multiplier has been designed using TSMC 180nm. The basic cells in multiplier are designed to have small propagation delay and delay variation. The hybrid wave-pipelined multiplier is able to achieve 2.86 billion multiplications per second.
Citation:
Suryanarayana B. Tatapudi, Jos? G. Delgado-Frias, "A High Performance Hybrid Wave-Pipelined Multiplier," isvlsi, pp.282-283, IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design (ISVLSI'05), 2005 Usage of this product signifies your acceptance of the Terms of Use. | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
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