RG-SRAM: A Low Gate Leakage Memory Design

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IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design (ISVLSI'05)

RG-SRAM: A Low Gate Leakage Memory Design (PDF)

Tampa, Florida

May 11-May 12

ISBN: 0-7695-2365-X

	ASCII Text	x
	Charan Thondapu, Praveen Elakkumanan, Ramalingam Sridhar, "RG-SRAM: A Low Gate Leakage Memory Design," VLSI, IEEE Computer Society Annual Symposium on, pp. 295-296, IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design (ISVLSI'05), 2005.

	BibTex	x
	@article{ 10.1109/ISVLSI.2005.64, author = {Charan Thondapu and Praveen Elakkumanan and Ramalingam Sridhar}, title = {RG-SRAM: A Low Gate Leakage Memory Design}, journal ={VLSI, IEEE Computer Society Annual Symposium on}, volume = {0}, year = {2005}, isbn = {0-7695-2365-X}, pages = {295-296}, doi = {http://doi.ieeecomputersociety.org/10.1109/ISVLSI.2005.64}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - VLSI, IEEE Computer Society Annual Symposium on TI - RG-SRAM: A Low Gate Leakage Memory Design SN - 0-7695-2365-X SP295 EP296 A1 - Charan Thondapu, A1 - Praveen Elakkumanan, A1 - Ramalingam Sridhar, PY - 2005 KW - null VL - 0 JA - VLSI, IEEE Computer Society Annual Symposium on ER -

Charan Thondapu, State University of New York at Buffalo

Praveen Elakkumanan, State University of New York at Buffalo

Ramalingam Sridhar, State University of New York at Buffalo

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ISVLSI.2005.64

The gate oxide thickness in sub-70nm process technologies approaches the limit where direct gate tunneling current starts to play a significant role in both off-state and on-state transistors. In this paper, we present a novel Reduced-Gate SRAM (RG-SRAM) that uses two additional PMOS pass transistors to decrease the gate leakage dissipation in Very Deep Sub-Micron (VDSM) cache and embedded memories.

Citation:

Charan Thondapu, Praveen Elakkumanan, Ramalingam Sridhar, "RG-SRAM: A Low Gate Leakage Memory Design," isvlsi, pp.295-296, IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design (ISVLSI'05), 2005

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