IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design (ISVLSI'05) PASSAT: Efficient SAT-Based Test Pattern Generation for Industrial Circuits Tampa, Florida May 11-May 12 ISBN: 0-7695-2365-X
Automatic Test Pattern Generation (ATPG) based on Boolean Satisfiability (SAT) has been proposed as an alternative to classical search algorithms. SAT-based ATPG turned out to be more robust and more effective by formulating the problem as a set of equations. In this paper we present an efficient ATPG algorithm that makes use of powerful SAT-solving techniques. Problem specific heuristics are applied to guide the search. In contrast to previous SAT-based algorithms, the new approach can also cope with tri-states. The algorithm has been implemented as the tool PASSAT. Experimental results on large industrial circuits are given to demonstrate the quality and efficiency of the algorithm.
Citation:
Junhao Shi, G?rschwin Fey, Rolf Drechsler, Andreas Glowatz, Friedrich Hapke, J? Schl?ffel, "PASSAT: Efficient SAT-Based Test Pattern Generation for Industrial Circuits," isvlsi, pp.212-217, IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design (ISVLSI'05), 2005 Usage of this product signifies your acceptance of the Terms of Use. | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
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