IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design (ISVLSI'05) Leakage Power Driven Behavioral Synthesis of Pipelined Datapaths Tampa, Florida May 11-May 12 ISBN: 0-7695-2365-X
We present a scheduling, allocation and binding methodology that employs MTCMOS as the standby leakage reduction mechanism. We use the simulated annealing meta-heuristic for optimizing leakage power. The cost functions for our approach are obtained after extensive characterization trials taking into account, the run-time characteristics of the MTCMOS approach. Our approach makes use of two cost factors: leakage cost, for optimizing the number of MTCMOS instances, and settling cost, for the minimization of their active-to-standby transitions. We enhance throughput and performance of the datapaths by synthesizing them as functionally pipelined systems before performing our optimizations. Using fully pre-characterized leakage libraries for RT-level simulation, we obtain an average leakage power reduction of 36.2%, and an average area overhead of 6.2%. However with a small increase in schedule latency we obtain an average reduction of around 3.95%-4.6% in the total area.
Citation:
Ranganath Gopalan, Chandramouli Gopalakrishnan, Srinivas Katkoori, "Leakage Power Driven Behavioral Synthesis of Pipelined Datapaths," isvlsi, pp.167-172, IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design (ISVLSI'05), 2005 Usage of this product signifies your acceptance of the Terms of Use. | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||