High Speed Redundant Adder and Divider in Output Prediction Logic

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	Similar Articles Articles by Xinyu Guo Articles by Carl Sechen

IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design (ISVLSI'05)

Tampa, Florida

May 11-May 12

ISBN: 0-7695-2365-X

	ASCII Text	x
	Xinyu Guo, Carl Sechen, "High Speed Redundant Adder and Divider in Output Prediction Logic," VLSI, IEEE Computer Society Annual Symposium on, pp. 34-41, IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design (ISVLSI'05), 2005.

	BibTex	x
	@article{ 10.1109/ISVLSI.2005.38, author = {Xinyu Guo and Carl Sechen}, title = {High Speed Redundant Adder and Divider in Output Prediction Logic}, journal ={VLSI, IEEE Computer Society Annual Symposium on}, volume = {0}, year = {2005}, isbn = {0-7695-2365-X}, pages = {34-41}, doi = {http://doi.ieeecomputersociety.org/10.1109/ISVLSI.2005.38}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - VLSI, IEEE Computer Society Annual Symposium on TI - High Speed Redundant Adder and Divider in Output Prediction Logic SN - 0-7695-2365-X SP34 EP41 A1 - Xinyu Guo, A1 - Carl Sechen, PY - 2005 KW - null VL - 0 JA - VLSI, IEEE Computer Society Annual Symposium on ER -

Xinyu Guo, University of Washington

Carl Sechen, University of Washington

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ISVLSI.2005.38

A redundant bit adder (RBA) and a divider, both implemented in output prediction logic (OPL), are presented. By combining the carry-free nature of the redundant number system and the high-speed characteristics of OPL, the performance of the arithmetic blocks was tremendously improved. Fabricated in 0.18 ?m/1.8V CMOS, the adder achieves a measured delay of 211ps (2.4 fanout-of-four inverter delays), which is significantly faster than any previously published RBAs. The divider implemented in the same technology can achieve an operating frequency of 1.25GHz.

Citation:

Xinyu Guo, Carl Sechen, "High Speed Redundant Adder and Divider in Output Prediction Logic," isvlsi, pp.34-41, IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design (ISVLSI'05), 2005

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