High Speed Max-Log-MAP Turbo SISO Decoder Implementation Using Branch Metric Normalization

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IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design (ISVLSI'05)

Tampa, Florida

May 11-May 12

ISBN: 0-7695-2365-X

	ASCII Text	x
	J. H. Han, A. T. Erdogan, T. Arslan, "High Speed Max-Log-MAP Turbo SISO Decoder Implementation Using Branch Metric Normalization," VLSI, IEEE Computer Society Annual Symposium on, pp. 173-178, IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design (ISVLSI'05), 2005.

	BibTex	x
	@article{ 10.1109/ISVLSI.2005.37, author = {J. H. Han and A. T. Erdogan and T. Arslan}, title = {High Speed Max-Log-MAP Turbo SISO Decoder Implementation Using Branch Metric Normalization}, journal ={VLSI, IEEE Computer Society Annual Symposium on}, volume = {0}, year = {2005}, isbn = {0-7695-2365-X}, pages = {173-178}, doi = {http://doi.ieeecomputersociety.org/10.1109/ISVLSI.2005.37}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - VLSI, IEEE Computer Society Annual Symposium on TI - High Speed Max-Log-MAP Turbo SISO Decoder Implementation Using Branch Metric Normalization SN - 0-7695-2365-X SP173 EP178 A1 - J. H. Han, A1 - A. T. Erdogan, A1 - T. Arslan, PY - 2005 KW - null VL - 0 JA - VLSI, IEEE Computer Society Annual Symposium on ER -

J. H. Han, University of Edinburgh

A. T. Erdogan, University of Edinburgh and Institute of System Level Integration

T. Arslan, University of Edinburgh and Institute of System Level Integration

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ISVLSI.2005.37

The authors present a turbo soft-in soft-out (SISO) decoder based on Max-Log maximum a posteriori (ML-MAP) algorithm implemented with sliding window (SW) method. A novel technique based on branch metric normalization is introduced to improve the speed performance of the decoder. The turbo decoder with the proposed technique has been synthesized to evaluate its power consumption and area usage using a 0.18um standard CMOS cell library. It is shown that while power consumption and area usage change slightly with our technique, it achieves up to 58% speed-up compared to a conventional SISO decoder architecture.

Citation:

J. H. Han, A. T. Erdogan, T. Arslan, "High Speed Max-Log-MAP Turbo SISO Decoder Implementation Using Branch Metric Normalization," isvlsi, pp.173-178, IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design (ISVLSI'05), 2005

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