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IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design (ISVLSI'05)
Design of a QCA Memory with Parallel Read/Serial Write
Tampa, Florida
May 11-May 12
ISBN: 0-7695-2365-X
M. Ottavi, Northeastern University Boston
V. Vankamamidi, Northeastern University Boston
F. Lombardi, Northeastern University Boston
S. Pontarelli, University of Rome
A. Salsano, University of Rome
This paper presents a novel memory architecture for implementation by Quantum-dot Cellular Automata (QCA). The proposed architecture combines the advantages of reduced area of a serial memory with the reduced latency in the read operation of a parallel memory. An extensive evaluation with respect to latency and area is pursued. For area analysis, a novel characterization which considers cells in the logic circuitry, interconnect as well as the unused portion of the Cartesian place as QCA layout, is proposed.
Citation:
M. Ottavi, V. Vankamamidi, F. Lombardi, S. Pontarelli, A. Salsano, "Design of a QCA Memory with Parallel Read/Serial Write," isvlsi, pp.292-294, IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design (ISVLSI'05), 2005
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