Design and Implementaion of a 2D-DCT Architecture Using Coefficient Distributed Arithmetic

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IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design (ISVLSI'05)

Tampa, Florida

May 11-May 12

ISBN: 0-7695-2365-X

	ASCII Text	x
	Soumik Ghosh, Soujanya Venigalla, Magdy Bayoumi, "Design and Implementaion of a 2D-DCT Architecture Using Coefficient Distributed Arithmetic," VLSI, IEEE Computer Society Annual Symposium on, pp. 162-166, IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design (ISVLSI'05), 2005.

	BibTex	x
	@article{ 10.1109/ISVLSI.2005.25, author = {Soumik Ghosh and Soujanya Venigalla and Magdy Bayoumi}, title = {Design and Implementaion of a 2D-DCT Architecture Using Coefficient Distributed Arithmetic}, journal ={VLSI, IEEE Computer Society Annual Symposium on}, volume = {0}, year = {2005}, isbn = {0-7695-2365-X}, pages = {162-166}, doi = {http://doi.ieeecomputersociety.org/10.1109/ISVLSI.2005.25}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - VLSI, IEEE Computer Society Annual Symposium on TI - Design and Implementaion of a 2D-DCT Architecture Using Coefficient Distributed Arithmetic SN - 0-7695-2365-X SP162 EP166 A1 - Soumik Ghosh, A1 - Soujanya Venigalla, A1 - Magdy Bayoumi, PY - 2005 KW - null VL - 0 JA - VLSI, IEEE Computer Society Annual Symposium on ER -

Soumik Ghosh, University of Louisiana at Lafayette

Soujanya Venigalla, University of Louisiana at Lafayette

Magdy Bayoumi, University of Louisiana at Lafayette

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ISVLSI.2005.25

The paper describes the design and implementation of an 8?8 2D DCT chip for use in low-power applications. The design exploits a Coefficient distributed arithmetic (CoDA) scheme as opposed to the prevalent data distributed arithmetic (DDA) schemes to achieve low power consumption. The architecture uses no ROMs and uses minimum number of additions by exploiting the redundancy in the adder arrays. The described architecture for the CoDA scheme is implemented on FPGA and has been fabricated on silicon. The fabricated chip computes 8?8 2D DCT @ 50 MHz consuming around 137mW of power.

Citation:

Soumik Ghosh, Soujanya Venigalla, Magdy Bayoumi, "Design and Implementaion of a 2D-DCT Architecture Using Coefficient Distributed Arithmetic," isvlsi, pp.162-166, IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design (ISVLSI'05), 2005

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