409ps 4.7 FO4 64b Adder Based on Output Prediction Logic in 0.18um CMOS

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IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design (ISVLSI'05)

Tampa, Florida

May 11-May 12

ISBN: 0-7695-2365-X

	ASCII Text	x
	Sheng Sun, Yi Han, Xinyu Guo, Kian Haur Chong, Larry McMurchie, Carl Sechen, "409ps 4.7 FO4 64b Adder Based on Output Prediction Logic in 0.18um CMOS," VLSI, IEEE Computer Society Annual Symposium on, pp. 52-58, IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design (ISVLSI'05), 2005.

	BibTex	x
	@article{ 10.1109/ISVLSI.2005.2, author = {Sheng Sun and Yi Han and Xinyu Guo and Kian Haur Chong and Larry McMurchie and Carl Sechen}, title = {409ps 4.7 FO4 64b Adder Based on Output Prediction Logic in 0.18um CMOS}, journal ={VLSI, IEEE Computer Society Annual Symposium on}, volume = {0}, year = {2005}, isbn = {0-7695-2365-X}, pages = {52-58}, doi = {http://doi.ieeecomputersociety.org/10.1109/ISVLSI.2005.2}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - VLSI, IEEE Computer Society Annual Symposium on TI - 409ps 4.7 FO4 64b Adder Based on Output Prediction Logic in 0.18um CMOS SN - 0-7695-2365-X SP52 EP58 A1 - Sheng Sun, A1 - Yi Han, A1 - Xinyu Guo, A1 - Kian Haur Chong, A1 - Larry McMurchie, A1 - Carl Sechen, PY - 2005 KW - null VL - 0 JA - VLSI, IEEE Computer Society Annual Symposium on ER -

Sheng Sun, University of Washington

Yi Han, University of Washington

Xinyu Guo, University of Washington

Kian Haur Chong, University of Washington

Larry McMurchie, University of Washington

Carl Sechen, University of Washington

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ISVLSI.2005.2

We present a fast 64b adder based on Output Prediction Logic (OPL) that has a measured worst-case delay of 409ps, equivalent to 4.7 FO4 inverter delays for the TSMC 0.18um process that was used for fabrication. This normalized delay is 1.45X faster than the fastest previously reported 64b adder. The adder uses a modified radix-3 Kogge-Stone architecture and has 5 logic levels.

Citation:

Sheng Sun, Yi Han, Xinyu Guo, Kian Haur Chong, Larry McMurchie, Carl Sechen, "409ps 4.7 FO4 64b Adder Based on Output Prediction Logic in 0.18um CMOS," isvlsi, pp.52-58, IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design (ISVLSI'05), 2005

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