A New Organization for a Perceptron-Based Branch Predictor and Its FPGA Implementation

I
ISVLSI
2005
IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design (ISVLSI'05)
Abstract - A New Organization for a Perceptron-Based Branch Predictor and Its FPGA Implementation

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	Similar Articles Articles by Oswaldo Cadenas Articles by Graham Megson Articles by Daniel Jones

IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design (ISVLSI'05)

A New Organization for a Perceptron-Based Branch Predictor and Its FPGA Implementation (PDF)

Tampa, Florida

May 11-May 12

ISBN: 0-7695-2365-X

	ASCII Text	x
	Oswaldo Cadenas, Graham Megson, Daniel Jones, "A New Organization for a Perceptron-Based Branch Predictor and Its FPGA Implementation," VLSI, IEEE Computer Society Annual Symposium on, pp. 305-306, IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design (ISVLSI'05), 2005.

	BibTex	x
	@article{ 10.1109/ISVLSI.2005.11, author = {Oswaldo Cadenas and Graham Megson and Daniel Jones}, title = {A New Organization for a Perceptron-Based Branch Predictor and Its FPGA Implementation}, journal ={VLSI, IEEE Computer Society Annual Symposium on}, volume = {0}, year = {2005}, isbn = {0-7695-2365-X}, pages = {305-306}, doi = {http://doi.ieeecomputersociety.org/10.1109/ISVLSI.2005.11}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - VLSI, IEEE Computer Society Annual Symposium on TI - A New Organization for a Perceptron-Based Branch Predictor and Its FPGA Implementation SN - 0-7695-2365-X SP305 EP306 A1 - Oswaldo Cadenas, A1 - Graham Megson, A1 - Daniel Jones, PY - 2005 KW - null VL - 0 JA - VLSI, IEEE Computer Society Annual Symposium on ER -

Oswaldo Cadenas, University of Reading

Graham Megson, University of Reading

Daniel Jones, University of Reading

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ISVLSI.2005.11

An unaltered rearrangement of the original computation of a neural based predictor at the algorithmic level is introduced as a new organization. Its FPGA implementation generates circuits that are 1.7 faster than a direct implementation of the original algorithm. This faster clock rate allows to implement predictors with longer history lengths using the nearly the same hardware budget.

Citation:

Oswaldo Cadenas, Graham Megson, Daniel Jones, "A New Organization for a Perceptron-Based Branch Predictor and Its FPGA Implementation," isvlsi, pp.305-306, IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design (ISVLSI'05), 2005

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