Autonomous Buffer Controller Design for Concurrent Execution in Block Level Pipelined Dataflow

I
ISVLSI
2004
IEEE Computer Society Annual Symposium on VLSI: Emerging Trends in VLSI Systems Design (ISVLSI'04)
Abstract - Autonomous Buffer Controller Design for Concurrent Execution in Block Level Pipelined Dataflow

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IEEE Computer Society Annual Symposium on VLSI: Emerging Trends in VLSI Systems Design (ISVLSI'04)

Autonomous Buffer Controller Design for Concurrent Execution in Block Level Pipelined Dataflow (PDF)

Lafayette, Louisiana

February 19-February 20

ISBN: 0-7695-2097-9

	ASCII Text	x
	Magesh Sadasivam, Sangjin Hong, "Autonomous Buffer Controller Design for Concurrent Execution in Block Level Pipelined Dataflow," VLSI, IEEE Computer Society Annual Symposium on, pp. 303, IEEE Computer Society Annual Symposium on VLSI: Emerging Trends in VLSI Systems Design (ISVLSI'04), 2004.

	BibTex	x
	@article{ 10.1109/ISVLSI.2004.1339565, author = {Magesh Sadasivam and Sangjin Hong}, title = {Autonomous Buffer Controller Design for Concurrent Execution in Block Level Pipelined Dataflow}, journal ={VLSI, IEEE Computer Society Annual Symposium on}, volume = {0}, year = {2004}, isbn = {0-7695-2097-9}, pages = {303}, doi = {http://doi.ieeecomputersociety.org/10.1109/ISVLSI.2004.1339565}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - VLSI, IEEE Computer Society Annual Symposium on TI - Autonomous Buffer Controller Design for Concurrent Execution in Block Level Pipelined Dataflow SN - 0-7695-2097-9 SP EP A1 - Magesh Sadasivam, A1 - Sangjin Hong, PY - 2004 KW - null VL - 0 JA - VLSI, IEEE Computer Society Annual Symposium on ER -

Magesh Sadasivam, State University of New York at Stony Brook

Sangjin Hong, State University of New York at Stony Brook

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ISVLSI.2004.1339565

This paper presents a method of generating configurable controller structure for concurrent processing of memory centric coarse grain data flows. The controller can be incorporated in both proposed block level pipelining and traditional fine grain pipelining. The proposed controller isolates controls for buffer and logic such that system integration is simplified while controllers are locally configured from orthogonal global information.

Citation:

Magesh Sadasivam, Sangjin Hong, "Autonomous Buffer Controller Design for Concurrent Execution in Block Level Pipelined Dataflow," isvlsi, pp.303, IEEE Computer Society Annual Symposium on VLSI: Emerging Trends in VLSI Systems Design (ISVLSI'04), 2004

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