A 64-bit Decimal Floating-Point Adder

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IEEE Computer Society Annual Symposium on VLSI: Emerging Trends in VLSI Systems Design (ISVLSI'04)

A 64-bit Decimal Floating-Point Adder (PDF)

Lafayette, Louisiana

February 19-February 20

ISBN: 0-7695-2097-9

	ASCII Text	x
	John Thompson, Nandini Karra, Michael J. Schulte, "A 64-bit Decimal Floating-Point Adder," VLSI, IEEE Computer Society Annual Symposium on, pp. 297, IEEE Computer Society Annual Symposium on VLSI: Emerging Trends in VLSI Systems Design (ISVLSI'04), 2004.

	BibTex	x
	@article{ 10.1109/ISVLSI.2004.1339563, author = {John Thompson and Nandini Karra and Michael J. Schulte}, title = {A 64-bit Decimal Floating-Point Adder}, journal ={VLSI, IEEE Computer Society Annual Symposium on}, volume = {0}, year = {2004}, isbn = {0-7695-2097-9}, pages = {297}, doi = {http://doi.ieeecomputersociety.org/10.1109/ISVLSI.2004.1339563}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - VLSI, IEEE Computer Society Annual Symposium on TI - A 64-bit Decimal Floating-Point Adder SN - 0-7695-2097-9 SP EP A1 - John Thompson, A1 - Nandini Karra, A1 - Michael J. Schulte, PY - 2004 KW - null VL - 0 JA - VLSI, IEEE Computer Society Annual Symposium on ER -

John Thompson, University of Wisconsin-Madison

Nandini Karra, University of Wisconsin-Madison

Michael J. Schulte, University of Wisconsin-Madison

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ISVLSI.2004.1339563

Due to rapid growth in financial, commercial, and Internet-based applications, there is an increasing desire to allow computers to operate on both binary and decimal floating-point numbers. Consequently, specifications for decimal floating-point support are being added to the IEEE-754 Standard for Floating-Point Arithmetic. In this paper, we present the design and implementation of a decimal floating-point adder that is compliant with the current draft revision of this standard. The adder supports operations on 64-bit (16-digit) decimal floating-point operands. We provide synthesis results indicating the estimated area and delay for our design when it is pipelined to various depths.

Citation:

John Thompson, Nandini Karra, Michael J. Schulte, "A 64-bit Decimal Floating-Point Adder," isvlsi, pp.297, IEEE Computer Society Annual Symposium on VLSI: Emerging Trends in VLSI Systems Design (ISVLSI'04), 2004

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