To address the excessive power during test, multiple scan divisions can be created such that not all the circuit blocks are active at the same time. While this concept has been successfully employed in the past for addressing shift power, the reported techniques for at-speed capture power reduction rely on modifications in the automatic test pattern generation (ATPG) algorithms. This paper shows how by analyzing the signal dependencies in the circuit’s sequential graph, scan chain divisions can be created automatically, such that power is guaranteed to be reduced during both shift and capture when Broadside test is employed. This is achieved with the existing ATPG flows and without affecting the transition fault coverage or increasing the scan time.