As processes shrink, the on-chip variability grows and this variation causes clock skew to rapidly consume a larger-and-larger percentage of the clock period. New techniques to reduce skew are required, but post-silicon clock adjustments will still be necessary to compensate for intra-die PVT variations. A relatively new technique for skew reduction, called Single-Edge Clocking (SEC), focuses clock buffer design on the critical edge by using alternating strong pull-up and strong pull-down buffers. In this paper, a new digitally tuned buffer for SEC clock networks is presented. It is based on a single-sided starved inverter configuration and is tuned using a 3-bit thermometer code. Sizing issues and skew reduction achievable in the presence of PVT variations are presented. The overhead in terms of layout area and current consumption for this new tunable buffer is only a small fraction of other tunable buffer designs.