9th International Symposium on Quality Electronic Design (isqed 2008) A Basis for Formal Robustness Checking March 17-March 19 ISBN: 978-0-7695-3117-5
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ISQED.2008.42
Correct input/output behavior of circuits in presence of internal malfunctions becomes more and more important. But reliable and efficient methods to measure this robustness are not available yet. In this paper a formal measure for the robustness of a circuit is introduced. Then, a first algorithm to determine the robustness is presented. This is done by reducing the problem either to sequential equivalence checking or to a sequence of property checking instances. The technique also identifies those parts of the circuit that are not robust from a functional point of view and therefore have to be hardened during layout.
Index Terms:
Robustness, Formal Methods, SAT, Fault models
Citation:
Goerschwin Fey, Rolf Drechsler, "A Basis for Formal Robustness Checking," isqed, pp.784-789, 9th International Symposium on Quality Electronic Design (isqed 2008), 2008 Usage of this product signifies your acceptance of the Terms of Use. | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||