Error-Tolerant SRAM Design for Ultra-Low Power Standby Operation

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	Similar Articles Articles by Huifang Qin Articles by Animesh Kumar Articles by Kannan Ramchandran Articles by Jan Rabaey Articles by Prakash Ishwar

9th International Symposium on Quality Electronic Design (isqed 2008)

March 17-March 19

ISBN: 978-0-7695-3117-5

	ASCII Text	x
	Huifang Qin, Animesh Kumar, Kannan Ramchandran, Jan Rabaey, Prakash Ishwar, "Error-Tolerant SRAM Design for Ultra-Low Power Standby Operation," Quality Electronic Design, International Symposium on, pp. 30-34, 9th International Symposium on Quality Electronic Design (isqed 2008), 2008.

	BibTex	x
	@article{ 10.1109/ISQED.2008.38, author = {Huifang Qin and Animesh Kumar and Kannan Ramchandran and Jan Rabaey and Prakash Ishwar}, title = {Error-Tolerant SRAM Design for Ultra-Low Power Standby Operation}, journal ={Quality Electronic Design, International Symposium on}, volume = {0}, year = {2008}, isbn = {978-0-7695-3117-5}, pages = {30-34}, doi = {http://doi.ieeecomputersociety.org/10.1109/ISQED.2008.38}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Quality Electronic Design, International Symposium on TI - Error-Tolerant SRAM Design for Ultra-Low Power Standby Operation SN - 978-0-7695-3117-5 SP30 EP34 A1 - Huifang Qin, A1 - Animesh Kumar, A1 - Kannan Ramchandran, A1 - Jan Rabaey, A1 - Prakash Ishwar, PY - 2008 KW - SRAM KW - leakage KW - DRV KW - low power KW - low voltage KW - ECC KW - error tolerant KW - variation VL - 0 JA - Quality Electronic Design, International Symposium on ER -

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ISQED.2008.38

We present an error-tolerant SRAM design optimized for ultra-low standby power. Using SRAM cell optimization techniques, the maximum data retention voltage (DRV) of a 90nm 26kb SRAM module is reduced from 550mV to 220mV. A novel error-tolerant architecture further reduces the minimum static-error-free VDD to 155mV. With a 100mV noise margin, a 255mV standby VDD effectively reduces the SRAM leakage power by 98% compared to the typical standby at 1V VDD.

Index Terms:

SRAM, leakage, DRV, low power, low voltage, ECC, error tolerant, variation

Citation:

Huifang Qin, Animesh Kumar, Kannan Ramchandran, Jan Rabaey, Prakash Ishwar, "Error-Tolerant SRAM Design for Ultra-Low Power Standby Operation," isqed, pp.30-34, 9th International Symposium on Quality Electronic Design (isqed 2008), 2008

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