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9th International Symposium on Quality Electronic Design (isqed 2008)
Feedback-Switch Logic (FSL): A High-Speed Low-Power Differential Dynamic-Like Static CMOS Circuit Family
March 17-March 19
ISBN: 978-0-7695-3117-5
ASCII Text
x 
 
Charbel J. Akl, Magdy A. Bayoumi, "Feedback-Switch Logic (FSL): A High-Speed Low-Power Differential Dynamic-Like Static CMOS Circuit Family," Quality Electronic Design, International Symposium on, pp. 385-390, 9th International Symposium on Quality Electronic Design (isqed 2008), 2008.
 
 
BibTex
x
 
@article{ 10.1109/ISQED.2008.36,
author = {Charbel J. Akl and Magdy A. Bayoumi},
title = {Feedback-Switch Logic (FSL): A High-Speed Low-Power Differential Dynamic-Like Static CMOS Circuit Family},
journal ={Quality Electronic Design, International Symposium on},
volume = {0},
year = {2008},
isbn = {978-0-7695-3117-5},
pages = {385-390},
doi = {http://doi.ieeecomputersociety.org/10.1109/ISQED.2008.36},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - Quality Electronic Design, International Symposium on
TI - Feedback-Switch Logic (FSL): A High-Speed Low-Power Differential Dynamic-Like Static CMOS Circuit Family
SN - 978-0-7695-3117-5
SP385
EP390
A1 - Charbel J. Akl,
A1 - Magdy A. Bayoumi,
PY - 2008
KW - circuit family
KW - high-speed
KW - low-power
VL - 0
JA - Quality Electronic Design, International Symposium on
ER -
 
We present a new dynamic-like static circuit family called Feedback-Switch Logic (FSL) that is suitable for high-speed low-power applications. FSL is a derivative of Cascode Voltage Switch Logic (CVSL) family. However, it does not suffer from the contention problems of clockless CVSL, and it consumes much less power than clocked CVSL (dual-rail domino). FSL gates offer fast switching, reduced capacitance, and input-switching dependent activity factor without the need of clock connection. An 18-bit majority voting circuit is simulated in a 90-nm technology, in order to compare static, clockless CVSL, dual-rail domino and FSL. Simulation results show that FSL reduces delay by 21% compared to static logic, and offers at least 46% power reduction compared to dynamic dual-rail domino logic with two-phase skew-tolerant clocking
Index Terms:
circuit family, high-speed, low-power
Citation:
Charbel J. Akl, Magdy A. Bayoumi, "Feedback-Switch Logic (FSL): A High-Speed Low-Power Differential Dynamic-Like Static CMOS Circuit Family," isqed, pp.385-390, 9th International Symposium on Quality Electronic Design (isqed 2008), 2008
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