9th International Symposium on Quality Electronic Design (isqed 2008) Finite-Point Gate Model for Fast Timing and Power Analysis March 17-March 19 ISBN: 978-0-7695-3117-5
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ISQED.2008.17
This paper proposes a new finite-point based approach for efficient characterization of CMOS gate. The new method identifies several key points on the I-V and Q-V curves to define the behavior of the static CMOS gate. It targets performance metrics such as timing, short-circuit power and leakage in the presence of process variations. Experimental results validate the accuracy of the new approach and yields simulation speeds more than 15X faster than BSIM based library characterization.
Citation:
Dinesh Ganesan, Alex Mitev, Janet Wang, Yu Cao, "Finite-Point Gate Model for Fast Timing and Power Analysis," isqed, pp.657-662, 9th International Symposium on Quality Electronic Design (isqed 2008), 2008 Usage of this product signifies your acceptance of the Terms of Use. | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
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