Due to scaling down of semiconductor technology, modern deep-submicron VLSI circuits are becoming increasingly vulnerable to noise from multiple sources, including cross-talk, radiation-induced single event transient, and power supply noises. Noise Rejection Curve (NRC) has been used as a metric to model noise susceptibility of logic circuits to such sources. In this paper an analytical model for NRC, which includes short channel effects, is presented. The model uses only basic SPICE parameters and does not include any calibration parameter. Comparison with SPICE simulations using TSMC 0.25um CMOS process parameters, suggests that the proposed model can accurately predict NRC characteristic of variety of logic circuits.