Designers require variational information for robust designs. Characterization of such information can be costly for thenovel nanoparticle interconnect process, which utilize nanoparticle silver solutions. To reduce characterization cost and initiate circuit level considerations for foldable electronics, we provide nanoparticle interconnect models. We use SEM measurements to characterize nanoparticle size distribution. We conduct field solver simulations over the proposed model to obtain physics-based process variation impact on a nanoparticle interconnect resistance. Such methodology can be helpful to aid designers for circuits based on novel transistors, such as organic TFTs on low cost foldable substrates.