Integrated circuits today rely on extensive re-use of precharacterized IP bocks and macro cells to meet the demand for high performance system on chip (SoC). In this paper we propose a methodology for characterization of IP blocks and macro cells for statistical timing analysis considering process variations and spatial correlations. We develop efficient models for capturing both inter-die and intra-die variations in devices and interconnects. Increasing variability of the process parameters in sub-nanometer designs requires instance-specific characterization of these design blocks. We propose a technique for instancespecific calibration of pre-characterized timing model. The proposed approach was evaluated on large industrial designs of 1.2M and 3.5M gates in 65nm technology and validated against SPICE for accuracy.