DFM, DFY, Debug and Diagnosis: The Loop to Ensure Yield

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8th International Symposium on Quality Electronic Design (ISQED'07)

DFM, DFY, Debug and Diagnosis: The Loop to Ensure Yield (PDF)

San Jose, California

March 26-March 28

ISBN: 0-7695-2795-7

	ASCII Text	x
	Srikanth Venkataraman, "DFM, DFY, Debug and Diagnosis: The Loop to Ensure Yield," Quality Electronic Design, International Symposium on, pp. 5, 8th International Symposium on Quality Electronic Design (ISQED'07), 2007.

	BibTex	x
	@article{ 10.1109/ISQED.2007.61, author = {Srikanth Venkataraman}, title = {DFM, DFY, Debug and Diagnosis: The Loop to Ensure Yield}, journal ={Quality Electronic Design, International Symposium on}, volume = {0}, year = {2007}, isbn = {0-7695-2795-7}, pages = {5}, doi = {http://doi.ieeecomputersociety.org/10.1109/ISQED.2007.61}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Quality Electronic Design, International Symposium on TI - DFM, DFY, Debug and Diagnosis: The Loop to Ensure Yield SN - 0-7695-2795-7 SP EP A1 - Srikanth Venkataraman, PY - 2007 KW - null VL - 0 JA - Quality Electronic Design, International Symposium on ER -

Srikanth Venkataraman, Intel

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ISQED.2007.61

Semiconductor yield has traditionally been limited by random particle-defect based issues.However, as the feature sizes reduced to 0.13 micron and below, systematic mechanism-limited yield loss began to appear as a substantial component in yield loss. In addition, it is becoming clear that ramping yield would take longer and final yields would not reach historical norms.

Citation:

Srikanth Venkataraman, "DFM, DFY, Debug and Diagnosis: The Loop to Ensure Yield," isqed, pp.5, 8th International Symposium on Quality Electronic Design (ISQED'07), 2007

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