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8th International Symposium on Quality Electronic Design (ISQED'07)
Device Footprint Scaling for Ultra Thin Body Fully Depleted SOI
San Jose, California
March 26-March 28
ISBN: 0-7695-2795-7
ASCII Text
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Jie Deng, Keunwoo Kim, Ching-Te Chuang, H.-S Philip Wong, "Device Footprint Scaling for Ultra Thin Body Fully Depleted SOI," Quality Electronic Design, International Symposium on, pp. 145-152, 8th International Symposium on Quality Electronic Design (ISQED'07), 2007.
 
 
BibTex
x
 
@article{ 10.1109/ISQED.2007.60,
author = {Jie Deng and Keunwoo Kim and Ching-Te Chuang and H.-S Philip Wong},
title = {Device Footprint Scaling for Ultra Thin Body Fully Depleted SOI},
journal ={Quality Electronic Design, International Symposium on},
volume = {0},
year = {2007},
isbn = {0-7695-2795-7},
pages = {145-152},
doi = {http://doi.ieeecomputersociety.org/10.1109/ISQED.2007.60},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - Quality Electronic Design, International Symposium on
TI - Device Footprint Scaling for Ultra Thin Body Fully Depleted SOI
SN - 0-7695-2795-7
SP145
EP152
A1 - Jie Deng,
A1 - Keunwoo Kim,
A1 - Ching-Te Chuang,
A1 - H.-S Philip Wong,
PY - 2007
KW - null
VL - 0
JA - Quality Electronic Design, International Symposium on
ER -
 
Jie Deng, Stanford University, USA
Keunwoo Kim, IBM T.J. Watson Research Center, USA
Ching-Te Chuang, IBM T.J. Watson Research Center, USA
H.-S Philip Wong, Stanford University, USA
We propose selective scaling of device footprint for 65 nm and beyond CMOS technologies. The benefits of selective scaling of device footprint are illustrated using an ultra-thin body (UTB) fully-depleted SOI (FD-SOI) transistor as an example. We study the effect of footprint scaling on device, circuit, and system level performance. A complete 2-D device structure is modeled for the numerical analysis. The results predict that an optimal footprint design can provide 30% smaller chip layout area, 20% faster speed and 10% less dynamic power on overall chip performance benchmarked with a 53-bit pipelined multiplier.
Citation:
Jie Deng, Keunwoo Kim, Ching-Te Chuang, H.-S Philip Wong, "Device Footprint Scaling for Ultra Thin Body Fully Depleted SOI," isqed, pp.145-152, 8th International Symposium on Quality Electronic Design (ISQED'07), 2007
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