Most of DFM emphasis has been placed on those so called "lithography critical layers" like diffusion, poly, contact and metal layers. However, "non-lithography-critical layers" impact on the manufacture and the yield has not been investigated well. This paper addresses the DFM issue for one of "non-lithography-critical layers", i.e. thick gate oxide layout in dual oxide product, which in this case impacts the product yield significantly. In this paper, a yield loss in a dual oxide FPGA product is analyzed, and the root cause is demonstrated and finally the DFM approaches for gate oxide design and layout are proposed.