8th International Symposium on Quality Electronic Design (ISQED'07) Defect Tolerance in Nanotechnology Switches Using a Greedy Reconfiguration Algorithm San Jose, California March 26-March 28 ISBN: 0-7695-2795-7
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ISQED.2007.55
Lithography based IC fabrication is rapidly approaching its limit in terms of feature size. The current alternative is nanotechnology based fabrication, which relies on self-assembly of nanotubes or nanowires. Such a process is subject to a high defect rate, which can be tolerated using carefully crafted defect tolerance techniques. This paper presents an algorithm for reconfiguration-based defect tolerance in nanotechnology switches. The algorithm offers an average switch density improvement of 50% to 100% to most recently published techniques.
Citation:
S. Ramsundar, Ahmad Al-Yamani, Dhiraj K. Pradhan, "Defect Tolerance in Nanotechnology Switches Using a Greedy Reconfiguration Algorithm," isqed, pp.807-813, 8th International Symposium on Quality Electronic Design (ISQED'07), 2007 Usage of this product signifies your acceptance of the Terms of Use. | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
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